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mc1451701 motorola 1 advance information
! !" cmos the n e w m c145170 1 i s p inforpi n c ompatibl e w it h t h e m c145170 . a comparison of the two parts is shown in the table below . the mc1451701 is recommended for new designs. the mc1451701 is a singlechip synthesizer capable of direct usage in the mf, hf , and vhf bands. a special architecture makes this pll the easiest to program in the industry . either a bit or byteoriented format may be used. due to the patented bitgrabber ? registers, no address/steering bits are required for random access of the three registers. thus, tuning can be accomplished via a 2byte serial transfer to the 16bit n register. the device features fully programmable r and n counters, an amplifier at the f in p in , o nchi p s uppor t o f a n e xterna l c rystal , a p rogrammabl e r eference output, and both single and doubleended phase detectors with linear transfer functions (no dead zones). a configuration (c) register allows the part to be configured t o m ee t v ariou s a pplications . a p atente d f eatur e a llow s t h e c register to shut off unused outputs, thereby minimizing noise and interference. in order to reduce lock times and prevent erroneous data from being loaded into the counters, a patented jamload feature is included. whenever a new divide r ati o i s l oade d i nt o t h e n r egister , b ot h t h e n a n d r c ounter s a re jamloaded with their respective values and begin counting down together . the phase detectors are also initialized during the jam load. ? operating voltage range: 2.5 to 5.5 v ? maximum operating frequency: 185 mhz @ v in = 500 mv pp, 4.5 v minimum supply 100 mhz @ v in = 500 mv pp, 3.0 v minimum supply ? operating supply current: 0.6 ma @ 3 v, 30 mhz 1.5 ma @ 3 v, 100 mhz 3.0 ma @ 5 v, 50 mhz 5.8 ma @ 5 v, 185 mhz ? operating temperature range: 40 to 85 c ? r counter division range: 1 and 5 to 32,767 ? n counter division range: 40 to 65,535 ? direct interface to motorola spi and national microwire ? serial data ports ? chip complexity: 4800 fets or 1200 equivalent gates ? see application note an1207/d comparision of the pll frequency synthesizers parameter mc1451701 mc145170 technology 1.2 m m cmos 1.5 m m cmos maximum frequency with 5 v 10% supply, f in 185 mhz 160 mhz maximum frequency with 5 v 10% supply, osc in 25 mhz 20 mhz maximum supply voltage 5.5 v 6.0 v maximum input capacitance, f in 7 pf 5 pf this document contains information on a new product. specifications and information herein are subject to change without notice. bitgrabber is a trademark of motorola inc. microwire is a trademark of national semiconductor corp. order this document by mc1451701/d semiconductor technical data f r ld v ss 9 10 11 12 f v v dd pd out 8 7 6 5 4 3 2 1 d out clk enb f in ref out osc out osc in 14 15 16 pin assignment d in f v p suffix plastic dip case 648 d suffix sog package case 751b ordering information MC145170P1 plastic dip mc145170d1 sog package mc145170dt1 tssop f r 16 1 13 dt suffix tssop case 948c 16 1 16 1 ? motorola, inc. 1996 rev 1 3/96
mc1451701 motorola 2 block diagram enb osc in d in clk osc out f in osc 1 2 7 5 4 input amp 3 15 16 15stage r counter 16stage n counter shift register and control logic por bitgrabber n register 16 bits bitgrabber c register 8 bits bitgrabber r register 15 bits phase/frequency detector b and control phase/frequency detector a and control lock detector and control 16 ld pd out f r f v 10 15 14 13 11 9 pin 16 = v dd pin 12 = v ss 6 4stage reference divider ref out 3 d out 8 f v control f r control f r f v maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 0.5 to + 5.5 v v in dc input voltage 0.5 to v dd + 0.5 v v out dc output voltage 0.5 to v dd + 0.5 v i in dc input current, per pin 10 ma i out dc output current, per pin 20 ma i dd dc supply current, v dd and v ss pins 30 ma p d power dissipation, per package 300 mw t stg storage temperature 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however , pre - cautions must be taken to avoid applications of any voltage higher than maximum rated volt - ages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
mc1451701 motorola 3 electrical characteristics (voltages referenced to v ss , t a = 40 to + 85 c) symbol parameter test condition v dd v guaranteed limit unit v dd power supply voltage range e 2.5 to 5.5 v v il maximum lowlevel input voltage* (d in , clk, enb , f in ) dc coupling to f in 2.5 4.5 5.5 0.50 1.35 1.65 v v ih minimum highlevel input voltage* (d in , clk, enb , f in ) dc coupling to f in 2.5 4.5 5.5 2.00 3.15 3.85 v v hys minimum hysteresis voltage (clk, enb ) 2.5 5.5 0.15 0.20 v v ol maximum lowlevel output voltage (any output) i out = 20 m a 2.5 5.5 0.1 0.1 v v oh minimum highlevel output voltage (any output) i out = 20 m a 2.5 5.5 2.4 5.4 v i ol minimum lowlevel output current (pd out , ref out , f r , f v , ld, f r , f v ) v out = 0.3 v v out = 0.4 v v out = 0.5 v 2.5 4.5 5.5 0.12 0.36 0.36 ma i oh minimum highlevel output current (pd out , ref out , f r , f v , ld, f r , f v ) v out = 2.2 v v out = 4.1 v v out = 5.0 v 2.5 4.5 5.5 0.12 0.36 0.36 ma i ol minimum lowlevel output current (d out ) v out = 0.4 v 4.5 1.6 ma i oh minimum highlevel output current (d out ) v out = 4.1 v 4.5 1.6 ma i in maximum input leakage current (d in , clk, enb , osc in ) v in = v dd or v ss 5.5 1.0 m a i in maximum input current (f in ) v in = v dd or v ss 5.5 120 m a i oz maximum output leakage current (pd out ) v in = v dd or v ss , output in highimpedance state 5.5 100 na (d out ) 5.5 5 m a i dd maximum quiescent supply current v in = v dd or v ss ; outputs open; excluding f in amp input current component 5.5 100 m a i dd maximum operating supply current f in = 500 mv pp; osc in = 1 mhz @ 1 v pp; ld, f r , f v , ref out = inactive and no connect; osc out , f v , f r , pd out = no connect; d in , enb, clk = v dd or v ss e ** ma * when dc coupling to the osc in pin is used, the pin must be driven railtorail. in this case, osc out should be floated. ** the nominal values at 3 v are 0.6 ma @ 30 mhz, and 1.5 ma @ 100 mhz. the nominal values at 5 v are 3.0 ma @ 50 mhz, and 5.8 ma @ 185 mhz. these are not guaranteed limits.
mc1451701 motorola 4 ac interface characteristics ( t a = 40 to + 85 c, c l = 50 pf, input t r = t f = 10 ns unless otherwise indicated) symbol parameter figure no. v dd v guaranteed limit unit f clk serial data clock frequency (note: refer to clock t w below) 1 2.5 4.5 5.5 dc to 3.0 dc to 4.0 dc to 4.0 mhz t plh , t phl maximum propagation delay, clk to d out 1, 5 2.5 4.5 5.5 150 85 85 ns t plz , t phz maximum disable time, d out active to high impedance 2, 6 2.5 4.5 5.5 300 200 200 ns t pzl , t pzh access time, d out high impedance to active 2, 6 2.5 4.5 5.5 0 to 200 0 to 100 0 to 100 ns t tlh , t thl maximum output transition time, d out cl = 50 pf 1, 5 2.5 4.5 5.5 150 50 50 ns cl = 200 pf 1, 5 2.5 4.5 5.5 900 150 150 ns c in maximum input capacitance d in , enb , clk e 10 pf c out maximum output capacitance d out e 10 pf timing requirements ( t a = 40 to + 85 c, input t r = t f = 10 ns unless otherwise indicated) symbol parameter figure no. v dd v guaranteed limit unit t su , t h minimum setup and hold times, d in vs clk 3 2.5 4.5 5.5 55 40 40 ns t su , t h , t rec minimum setup, hold, and recovery t imes, enb vs clk 4 2.5 4.5 5.5 135 100 100 ns t w(h) minimum inactivehigh pulse width, enb 4 2.5 4.5 5.5 400 300 300 ns t w minimum pulse width, clk 1 2.5 4.5 5.5 166 125 125 ns t r , t f maximum input rise and fall times, clk 1 2.5 4.5 5.5 100 100 100 m s
mc1451701 motorola 5 switching waveforms 10% v dd v ss 1/f clk d out clk 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r figure 1. enb d out d out 50% v dd v ss 50% t pzh t pzl t plz 50% t phz figure 2. 10% 90% v dd v ss high impedance high impedance d in clk 50% valid 50% t su t h v dd v ss v dd v ss figure 3. clk enb 50% t su t h first clk last clk t rec 50% figure 4. v dd v ss v dd v ss t w(h) test point device under test c l * * includes all probe and fixture capacitance. figure 5. test circuit test point device under test c l * * includes all probe and fixture capacitance. figure 6. test circuit 7.5 k w connect to v dd when testing t plz and t pzl . connect to v ss when testing t phz and t pzh .
mc1451701 motorola 6 loop specifications ( t a = 40 to + 85 c) symbol parameter test condition figure no. v dd v guaranteed range unit symbol parameter test condition figure no. dd v min max unit f input frequency, f in v in 500 mv pp sine wave, n counter set to divide ratio such that f v 2 mhz 7 2.5 3.0 4.5 5.5 5* 5* 25* 45* tbd 100 185 185 mhz f input frequency, osc in externally driven with accoupled signal v in 1 v pp sine wave, osc out = no connect, r counter set to divide ratio such that f r 2 mhz 8 2.5 3.0 4.5 5.5 1* 1* 1* 1* 12 14 25 25 mhz f xtal crystal frequency , osc in and osc out c1 30 pf c2 30 pf includes stray capacitance 9 2.5 3.0 4.5 5.5 2 2 2 2 12 12 15 15 mhz f out output frequency, ref out c l = 30 pf 10, 12 2.5 4.5 5.5 dc dc dc tbd 10 10 mhz f operating frequency of the phase detectors 2.5 4.5 5.5 dc dc dc tbd 2 2 mhz t w output pulse width, f r , f v , and ld f r in phase with f v c l = 50 pf 11, 12 2.5 4.5 5.5 tbd 20 16 tbd 100 90 ns t tlh , t thl output transition times, f r , f v , ld, f r , and f v c l = 50 pf 11, 12 2.5 4.5 5.5 e e e tbd 65 60 ns c in input capacitance f in osc in e e e e e e 7 7 pf * if lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in accoupled case. also, see figure 22 for dc decoupling.
mc1451701 motorola 7 sine wave generator 100 pf mc1451701 test point v+ v dd f in f v v in 50 w * figure 7. test circuit sine wave generator 50 w 0.01 m f test point v dd osc in f r v in figure 8. test circuit c1 test point v dd ref out v ss osc in osc out c2 figure 9. test circuit 50% ref out 1/f ref out figure 10. switching waveform 10% 90% output t tlh t thl figure 11. switching waveform 50% t w test point device under test c l * * includes all probe and fixture capacitance. figure 12. test circuit v ss v+ v ss v+ mc1451701 osc out mc1451701 output * characteristic impedance 10 m w
mc1451701 motorola 8 pin descriptions digital interface pins d in serial data input (pin 5) the bit stream begins with the most significant bit (msb) and is shifted in on the lowtohigh transition of clk. the bit pattern is 1 byte (8 bits) long to access the c or configuration register, 2 bytes (16 bits) to access the n register, or 3 bytes (24 bits) to access the r register . additionally, the r register can be accessed with a 15bit transfer (see table 1). an op- tional pattern which resets the device is shown in figure 13. the values in the c, n, and r registers do not change during shifting because the transfer of data to the registers is con - trolled by enb . the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the three registers. random access of any register is provided (i.e., the registers may be accessed in any sequence). data is retained in the registers over a supply range of 2.5 to 5.5 v . the formats are shown in figures 13, 14, 15, and 16. d in typically switches near 50% of v dd to maximize noise immunity. this input can be directly interfaced to cmos de - vices w it h o utput s g uarantee d t o s witc h n ear r ailtorail. when i nterfacin g t o n mo s o r t t l d evices , e ithe r a l evel shifter (mc74hc14a, mc14504b) or pullup resistor of 1 to 10 k w must be used. parameters to consider when sizing the resistor are worstcase i ol of the driving device, maximum tolerable power consumption, and maximum data rate. table 1. register access (msbs are shifted in first, c0, n0, and r0 are the lsbs) number of clocks accessed register bit nomenclature 4 + 5 8 16 15 or 24 other values 32 values > 32 (reset) c register n register r register none see figures 24 e 31 c7, c6, c5, . . ., c0 n15, n14, n13, . . ., n0 r14, r13, r12, . . ., r0 clk serial data clock input (pin 7) lowtohigh transitions on clock shift bits available at d in , while hightolow transitions shift bits from d out . the chip's 161/2stage s hif t r egiste r i s s tatic , a llowin g c loc k r ates down to dc in a continuous or intermittent mode. four clock cycles followed by five clock cycles are needed to reset the device; this is optional. eight clock cycles are re - quired t o a cces s t h e c r egister . s ixtee n c loc k c ycle s a re needed for the n register . either 15 or 24 cycles can be used to access the r register (see t able 1 and figures 13, 14, 15, and 16). for cascaded devices, see figures 24 e 31. clk t ypicall y s witche s n ea r 5 0% o f v dd a n d h a s a schmitttriggered input buf fer . slow clk rise and fall times are allowed. see the last paragraph of d in for more informa- tion. note to guarantee proper operation of the poweron reset (por) circuit, the clk pin must be held at the potential of either the v ss or v dd pin during power up. that is, the clk input should not be floated or toggled while the v dd pin is ramping from 0 to at least 2.5 v . if control of the clk pin is not practical during power up, the initialization se - quence shown in figure 13 must be used. enb activelow enable input (pin 6) this pin is used to activate the serial interface to allow the transfer of data to/from the device. when enb is in an inac- tive high state, shifting is inhibited, d out is forced to the high impedance state, and the port is held in the initialized state. to transfer data to the device, enb (which must start inactive high) is taken low, a serial transfer is made via d in and clk, and enb is taken back high. the lowtohigh transition on enb transfers data to the c, n, or r register depending on the data stream length per table 1. note transitions on enb must not be attempted while clk is high. this puts the device out of synchro- nization with the microcontroller . resynchroniza- tion occurs when enb is high and clk is low. this i npu t i s a ls o s chmitttriggered a n d s witche s n ear 50% of v dd , thereby minimizing the chance of loading erro- neous data into the registers. see the last paragraph of d in for more information. d out threestate serial data output (pin 8) data is transferred out of the 161/2stage shift register through d out on the hightolow transition of clk. this out- put is a no connect, unless used in one of the manners dis - cussed below. d out could be fed back to an mcu/mpu to perform a wrap around test of serial data. this could be part of a system check conducted at power up to test the integrity of the sys - tem's processor, pc board traces, solder joints, etc. the pin could be monitored at an inline qa test during board manufacturing. finally, d out facilitates troubleshooting a system and per - mits cascading devices. reference pins osc in /osc out reference oscillator input/output (pins 1, 2) these pins form a reference oscillator when connected to terminals o f a n e xterna l p arallelresonan t c rystal. f re- quencysetting capacitors of appropriate values as recom - mended by the crystal supplier are connected from each pin to ground (up to a maximum of 30 pf each, including stray capacitance). an external feedback resistor of 1 to 15 m w is connected directly across the pins to ensure linear operation of t h e a mplifier . t h e r equire d c onnection s f o r t h e c ompo- nents are shown in figure 9.
mc1451701 motorola 9 if desired, an external clock source can be ac coupled to osc in . a 0.01 m f coupling capacitor is used for measure - ment purposes and is the minimum size recommended for applications. an external feedback resistor of approximately 10 m w is required across the o sc in and o sc out pins in the accoupled case (see figure 8). osc out is an internal node on the device and should not be used to drive any loads (i.e., osc out is unbuffered). however, the buffered ref out is available to drive external loads. the external signal level must be at least 1 v pp; the maximum frequencies are given in the loop specifications table. t hes e m aximum f requencie s a ppl y f o r r c ounter divide ratios as indicated in the table. for very small ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum input frequency of 2 mhz.) if an external source is available which swings railtorail (v dd t o v ss ) , t he n d c c ouplin g c a n b e u sed . i n t h e d c coupled c ase , n o e xterna l f eedbac k r esisto r i s n eeded. osc out must be a no connect to avoid loading an internal node on the device, as noted above. for frequencies below 1 mhz, dc coupling must be used. the r counter is a static counter and may be operated down to dc. however , wave shaping by a cmos buf fer may be required to ensure fast rise and fall times into the osc in pin. see figure 22. each rising edge on the osc in pin causes the r counter to decrement by one. ref out reference frequency output (pin 3) this output is the buffered output of the crystalgenerated reference frequency or externally provided reference source. this output may be enabled, disabled, or scaled via bits in the c register (see figure 14). ref out can be used to drive a microprocessor clock input, thereby s avin g a c rystal . u po n p owe r u p , t h e o nchip poweroninitialize c ircui t f orce s r ef out t o t he o sc in dividedby8 mode. ref out is capable of operation to 10 mhz; see the loop specifications table. therefore, divide values for the refer- ence divider are restricted to two or higher for osc in fre - quencies above 10 mhz. if unused, the pin should be floated and should be disabled via the c register to minimize dynamic power consumption and electromagnetic interference (emi). counter output pins f r r counter output (pin 9) this signal is the buffered output of the 15stage r count- er. f r can be enabled or disabled via the c register (pat - ented). the output is disabled (static low logic level) upon power up. if unused, the output should be left disabled and unconnected to minimize interference with external circuitry. the f r signal can be used to verify the r counter 's divide ratio. this ratio extends from 5 to 32,767 and is determined by the binary value loaded into the r register . also, direct access to the phase detector via the osc in pin is allowed by choosing a divide value of 1 (see figure 15). the maximum frequency w hic h t h e p hase d etector s o perat e i s 2 m hz. therefore, the frequency of f r must not exceed 2 mhz. when activated, the f r signal appears as normally low and pulses high. f v n counter output (pin 10) this signal is the buffered output of the 16stage n count- er. f v can be enabled or disabled via the c register (pat - ented). the output is disabled (static low logic level) upon power up. if unused, the output should be left disabled and unconnected to minimize interference with external circuitry. the f v signal can be used to verify the n counter 's divide ratio. this ratio extends from 40 to 65,535 and is determined by the binary value loaded into the n register. the maximum frequency w hic h t h e p hase d etector s o perat e i s 2 m hz. therefore, the frequency of f v must not exceed 2 mhz. when activated, the f v signal appears as normally low and pulses high. loop pins f in frequency input (pin 4) this pin is a frequency input from the vco. this pin feeds the onchip amplifier which drives the n counter. this signal is normally sourced from an external voltagecontrolled os - cillator (vco), and is accoupled into f in . a 100 pf coupling capacitor is used for measurement purposes and is the mini- mum size recommended for applications (see figure 7). the frequency capability of this input is dependent on the supply voltage as listed in the loop specifications table. for small divide ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum frequency of 2 mhz.) for signals which swing from at least the v il to v ih levels listed in the electrical characteristics table, dc coupling may be used. also, for low frequency signals (less than the minimum f requencie s s how n i n t he loo p s pecifications table), dc coupling is a requirement. the n counter is a static counter and may be operated down to dc. however , wave shaping by a cmos buf fer may be required to ensure fast rise and fall times into the f in pin. see figure 22. each rising edge on the f in pin causes the n counter to decrement by 1. pd out singleended phase/frequency detector output (pin 13) this is a threestate output for use as a loop error signal when combined with an external lowpass filter . through use of a motorola patented technique, the detector' s dead zone has been eliminated. therefore, the phase/frequency detec - tor is characterized by a linear transfer function. the opera - tion of the phase/frequency detector is described below and is shown in figure 17. pol bit (c7) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : negative pulses from high impedance frequency of f v < f r or phase of f v lagging f r : positive pulses from high impedance frequency and phase of f v = f r : essentially highimpe dance state; voltage at pin determined by loop filter pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : positive pulses from high impedance frequency of f v < f r or phase of f v lagging f r : negative pulses from high impedance frequency and phase of f v = f r : essentially highimpe dance state; voltage at pin determined by loop filter
mc1451701 motorola 10 this output can be enabled, disabled, and inverted via the c register. if desired, pd out can be forced to the highimpe dance state by utilization of the disable feature in the c regis - ter (patented). f r and f v doubleended phase/frequency detector outputs (pins 14, 15) these outputs can be combined externally to generate a loop error signal. through use of a motorola patented tech - nique, the detector's dead zone has been eliminated. there - fore, t h e p hase/frequenc y d etecto r i s c haracterize d b y a linea r t ransfe r f unction . t h e o peratio n o f t h e p hase/fre- quency d etecto r i s d escribe d b elo w a n d i s s how n i n f ig- ure 17. pol bit (c7) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : f v = nega - tive pulses, f r = essentially high frequency of f v < f r or phase of f v lagging f r : f v = essen - tially high, f r = negative pulses frequency and phase of f v = f r : f v and f r remain essen - tially high, except for a small minimum time period when both pulse low in phase pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : f r = nega - tive pulses, f v = essentially high frequency of f v < f r or phase of f v lagging f r : f r = essen - tially high, f v = negative pulses frequency and phase of f v = f r : f v and f r remain essen - tially high, except for a small minimum time period when both pulse low in phase these o utput s c a n b e e nabled , d isabled , a n d i nter- changed via the c register (patented). ld lock detector output (pin 11) this output is essentially at a high level with narrow low going pulses when the loop is locked (f r and f v of the same phase and frequency). the output pulses low when f v and f r are out of phase or different frequencies (see figure 17). this output can be enabled and disabled via the c register (patented). u po n p owe r u p , o nchi p i nitializatio n c ircuitry disables ld to a static low logic level to prevent a false alocko signal. if unused, ld should be disabled and left open. power supply v dd most positive supply potential (pin 16) this pin may range from + 2.5 to 5.5 v with respect to v ss . for optimum performance, v dd should be bypassed to v ss using lowinductance capacitor(s) mounted very close to the device. lead lengths on the capacitor(s) should be minimized . ( th e v er y f as t s witching s peed o f t h e d evice causes current spikes on the power leads.) v ss most negative supply potential (pin 12) this pin is usually ground. for measurement purposes, the v ss pin is tied to a ground plane. enb clk d in power up 1 2 3 4 5 1 2 3 4 note: this initialization sequence must be used immediately after power up if control of the clk pin is not possible. that is, if clk (pin 7) toggles or floats upon power up, use the above sequence to reset the device. also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to below 2.5 v , but not down to 0 v (for example, the supply drops down to 1 v). this is necessary because the onchip poweron reset is only activated when the supply ramps up from 0 v . zeroes don't cares don't cares one zeroes zero figure 13. reset sequence
mc1451701 motorola 11 enb clk d in msb lsb c7 c6 c5 c4 c3 c2 c1 c0 1 2 3 4 5 6 7 8 * * at this point, the new byte is transferred to the c register and stored. no other registers are affected. c7 e pol: selects the output polarity of the phase/frequency detectors. when set high, this bit inverts pd out and interchanges the f r function with f v as depicted in figure 17. also see the phase detector output pin descriptions for more information. this bit is cleared low at power up. c6 e pda/b: selects which phase/frequency detector is to be used. when set high, enables the output of phase/frequency detector a (pd out ) and disables phase/frequency detector b by forcing f r and f v to the static high state. when cleared low , phase/frequency detector b is enabled ( f r and f v ) and phase/frequency detector a is disabled with pd out forced to the highimpedance state. this bit is cleared low at power up. c5 e lde: enables the lock detector output when set high. when the bit is cleared low , the ld output is forced to a static low level. this bit is cleared low at power up. c4 c2, osc2 osc0: reference output controls which determine the ref out characteristics as shown below . upon power up, the bits are initialized such that osc in /8 is selected. c4 c3 c2 ref out frequency 0 0 0 dc (static low) 0 0 1 osc in 0 1 0 osc in /2 0 1 1 osc in /4 1 0 0 osc in /8 1 0 1 osc in /16 1 1 0 osc in /8 1 1 1 osc in /16 c1 e f v e: enables the f v output when set high. when cleared low , the f v output is forced to a static low level. the bit is cleared low upon power up. c0 e f r e: enables the f r output when set high. when cleared low , the f r output is forced to a static low level. the bit is cleared low upon power up. figure 14. c register access and format (8 clock cycles are used)
mc1451701 motorola 12 ?? ?? ?? ?? ?? ?? ?? x ?? ?? ?? x ?? ?? ?? x ?? ?? ?? x ?? ?? ?? x ?? ?? ?? x ?? ?? ?? x ?? ?? ?? ?? x ?? ?? ?? r14 ?? ?? ?? ?? r13 ?? ?? ?? r12 ?? ?? ?? r11 ?? ?? ?? r10 ?? ?? ?? r9 ?? ?? ?? ?? r8 ?? ?? ?? r7 ?? ?? ?? ?? r6 ?? ?? ?? r5 ?? ?? ?? ?? r4 ?? ?? ?? r3 ?? ?? ?? r2 ?? ?? ?? r1 ?? ?? ?? ?? ?? r0 ?? ?? ?? ?? ?? ?? x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 msb lsb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 not allowed r counter = 1 (direct access to reference side of phase/frequency detect or) not allowed not allowed not allowed r counter = 5 r counter = 6 r counter = 7 . . . f f . . . f f . . . e f r counter = 32,766 r counter = 32,767 hexadecimal v alue clk d 0 0 0 0 0 0 0 0 . . . 7 7 don't care bits see below see below see below see below ?? ?? ?? r14 ?? ?? ?? ?? r13 ?? ?? ?? r12 ?? ?? ?? ?? r11 ?? ?? ?? r10 ?? ?? ?? r9 ?? ?? ?? r8 ?? ?? ?? r7 ?? ?? ?? r6 ?? ?? ?? r5 ?? ?? ?? ?? r4 ?? ?? ?? r3 ?? ?? ?? ?? r2 ?? ?? ?? r1 ?? ?? ?? ?? ?? r0 ?? ?? ?? ?? ?? ?? lsb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 msb octal v alue decimal equiv alent in enb clk d in * * * at this point, the new data is transferred to the r register and stored. no other registers are af fected. enb figure 15. r register access and formats (either 24 or 15 clock cycles can be used)
mc1451701 motorola 13 enb clk d in 1 2 3 4 5 6 7 8 msb lsb n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 n11 n12 n13 n14 n15 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 0 0 0 0 f f 0 0 0 0 2 2 2 2 2 2 2 f f 0 1 2 3 5 6 7 8 9 a b e f not allowed not allowed not allowed not allowed not allowed not allowed not allowed n counter = 40 n counter = 41 n counter = 42 n counter = 43 n counter = 65,534 n counter = 65,535 hexadecimal value 0 0 0 0 0 0 0 0 0 0 0 f f decimal equivalent ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * * at this point, the two new bytes are transferred to the n register and stored. no other registers are af fected. in addition, the n and r counters are jamloaded and begin counting down together . figure 16. n register access and format (16 clock cycles are used) note: the pd out generates error pulses during outoflock conditions. when locked in phase and frequency , the output is high impedance and the voltage at that pin is determined by the lowpass filter capacitor . pd out , f r , and f v are shown with the polarity bit (pol) = low; see figure 14 for pol. f r reference osc in r f v feedback (f in n) pd out f r f v ld v h v l v h v h v h v l high impedance v h v l v l v l v h v l v h = high voltage level v l = low voltage level *at this point, when both f r and f v are in phase, both the sinking and sourcing output fet s are turned on for a very short interval. * figure 17. phase/frequency detectors and lock detector output waveforms
mc1451701 motorola 14 design considerations crystal oscillator considerations the following options may be considered to provide a ref - erence f requenc y t o m otorola' s c mo s f requenc y s ynthe- sizers. use of a hybrid crystal oscillator commercially available temperaturecompensated crystal oscillators (tcxos) or crystalcontrolled data clock oscilla - tors provide very stable reference frequencies. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to osc in . if the oscillator does not have cmos logic l evel s o n t h e o utputs , c apacitiv e o r a c c ouplin g t o osc in may be used (see figure 8). for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an offchip reference the user may design an of fchip crystal oscillator using discrete transistors or ics specifically developed for crystal oscillator applications, such as the mc12061 mecl device. the reference signal from the mecl device is ac coupled to osc in (see figure 18). for large amplitude signals (standard cmos logic levels), dc coupling is used. use of the onchip oscillator circuitry the onchip amplifier (a digital inverter) along with an ap - propriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the d esire d o perating f requency , s houl d b e c onnecte d a s shown in figure 18. the crystal should be specified for a loading capacitance (c l ) which does not exceed 20 pf when used at the highest operating f requencie s l iste d i n t he loo p s pecifications table. larger c l values are possible for lower frequencies. assuming r1 = 0 w , the shunt load capacitance (c l ) pres - ented across the crystal can be estimated to be: c l = c in c out c in + c out c1 ? c2 c1 + c2 + c a + c stray + where c in = 5 pf (see figure 19) c out = 6 pf (see figure 19) c a = 1 pf (see figure 19) c1 and c2 =external capacitors (see figure 18) c stray = the total equivalent external circuit stray capaci tance appearing across the crystal terminals the oscillator can be atrimmedo onfrequency by making a portion or all of c1 variable. the crystal and associated com - ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. circuit stray capacitance can also be handled by adding the appropriate stray value to the values for c in and c out . for this approach, the term c stray becomes 0 in the above expression for c l . power is dissipated in the ef fective series resistance of the crystal, r e , in figure 20. the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency . r1 in figure 18 limits the drive level. the use of r1 is not necessary in most cases. to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output fre - quency at the ref out pin (osc out is not used because load - ing impacts the oscillator). the frequency should increase very slightly as the dc supply voltage is increased. an over - driven crystal decreases in frequency or becomes unstable with an increase in supply voltage. the operating supply volt - age must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the os- cillator startup time is proportional to the value of r1. through t he p roces s o f s upplyin g c rystal s f o r u s e w ith cmo s i nverters , m an y c rystal m anufacturer s h av e d evel- oped expertise in cmos oscillator design with crystals. dis - cussions w it h s uc h m anufacturer s c an p rov e v er y h elpful (see table 2). r1* c2 c1 frequency synthesizer osc out osc in r f * may be needed in certain cases. see text. figure 18. pierce crystal oscillator circuit figure 19. parasitic capacitances of the amplifier and c stray c in c out c a osc in osc out c stray figure 20. equivalent crystal networks note: values are supplied by crystal manufacturer (parallel resonant crystal). 2 1 2 1 2 1 r s l s c s r e x e c o
mc1451701 motorola 15 recommended reading technical note tn24, statek corp. technical note tn7, statek corp. e. hafner , athe piezoelectric crystal unitdefinitions and method of measuremento, proc. ieee, v ol. 57, no. 2, feb. 1969. d. k emper , l . r osine , a quart z c rystal s f o r f requency controlo, electrotechnology , june 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design , may 1966. d. babin, adesigning crystal oscillatorso, machine design , march 7, 1985. d. b abin , a guideline s f o r c rysta l o scillato r d esigno, machine design , april 25, 1985. table 2. partial list of crystal manufacturers name address phone united states crystal corp. crystek crystal statek corp. fox electronics 3605 mccart ave., ft. worth, tx 76110 2351 crystal dr., ft. myers, fl 33907 512 n. main st., orange, ca 92668 5570 enterprise parkway, ft. myers, fl 33905 (817) 9213013 (813) 9362109 (714) 6397810 (813) 6930099 note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers.
mc1451701 motorola 16 f(s) = assuming gain a is very large, then: f(s) = z = w n = phaselocked loop e low pass filter design (c) a c r 2 c vco (a) f r f v r 1 r 2 k f k vco nr 1 c r 1 sc + 1 w n = z = w n r 2 c 2 r 2 sc + 1 r 1 sc note: for (c), r 1 is frequently split into two series resistors; each resistor is equal to r 1 divided by 2. a capacitor c c is then placed from the midpoint to ground to further filter the error pulses. the value of c c should be such that the corner frequency of this network does not significantly affect w n . definitions: n = t otal division ratio in feedback loop k f (phase detector gain) = v dd / 4 p v/radian for pd out k f (phase detector gain) = v dd / 2 p v/radian for f v and f r k vco (vco gain) = 2 pd f vco d v vco for a nominal design starting point, the user might consider a damping factor z 0.7 and a natural loop frequency w n (2 p f r /50) where f r is the frequency at the phase detector input. larger w n values result in faster loop lock times and, for similar sideband filtering, higher f r related vco sidebands. recommended reading: gardner, floyd m., phaselock techniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. seidman, arthur h., integrated circuits applications handbook , chapter 17, pp. 538586. new y ork, john wiley & sons. fadrhons, jan, adesign and analyze plls on a programmable calculator ,o edn . march 5, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. an1207, the mc145170 in basic hf and vhf oscillators, motorola semiconductor products, inc., 1992. + 1 c vco pd out n w n 2k f k vco f(s) = z = w n = (b) (r 1 + r 2 )sc + 1 r 2 sc + 1 c vco r 2 pd out r 1 r 1 r 1 k f k vco nc(r 1 + r 2 ) r 2 c + n k f k vco k f k vco ncr 1 0.5 w n
mc1451701 motorola 17 mcu threshold detector osc in v dd f in osc out f v f r v ss f r ld enb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vhf output buffer optional ref out d in d out pd out v+ integrator vhf vco lowpass filter v+ optional loop error signals (note 1) mc1451701 clk f v optional (note 4) notes: 1. the f r and f v outputs are fed to an external combiner/loop filter. see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . 2. for optimum performance, bypass the v dd pin to v ss (gnd) with one or more lowinduc - tance capacitors. 3. the r counter is programmed for a divide value = osc in /f r . t ypically , f r is the tuning resolu - tion required for the vco. also, the vco frequency divided by f r = n, where n is the divide value of the n counter. 4. may be an rc lowpass filter. figure 21. example application
mc1451701 motorola 18 osc in f in osc out v ss v+ note: the signals at points a and b may be lowfrequency sinusoidal or square waves with slow edge rates or noisy signal edges. at points c and d, the signals are cleaned up, have sharp edge rates, and railtorail signal swings. with signals as described at points c and d, the mc1451701 is guaranteed to operate down to a frequency as low as dc. figure 22. low frequency operation using dc coupling c d a b no connect mc74hc14a mc1451701 v dd
mc1451701 motorola 19 4 1 3 2 f in (pin 4) sog package marker frequency (mhz) resistance ( w ) reactance ( w ) capacitance (pf) 1 5 2390 5900 5.39 2 100 39.2 347 4.58 3 150 25.8 237 4.48 4 185 42.6 180 4.79 figure 23. input impedance at f in e series format (r + jx) (5 mhz to 185 mhz) cmos mcu d out enb clk d in device #1 mc1451701 enb clk d in optional device #2 mc1451701 d out 33 k w note 1 notes: 1. the 33 k w resistor is needed to prevent the d in pin from floating. (the d out pin is a threestate output.) 2. see related figures 25, 26, and 27. figure 24. cascading two mc1451701 devices
mc1451701 motorola 20 1 2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 33 34 39 40 c register bits of device #2 in figure 24 c register bits of device #1 in figure 24 *at this point, the new data is transferred to the c registers of both devices and stored. no other registers are af fected. x x x x x x c7 c6 c0 x x x c7 c6 c0 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? * enb clk d in figure 25. accessing the c registers of two cascaded mc1451701 devices enb clk d in 1 2 8 9 10 25 26 27 30 31 39 40 41 42 44 45 r register bits of device #2 in figure 24 r register bits of device #1 in figure 24 x x x x r14 r13 x r14 r11 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 48 49 50 55 56 r7 r6 r0 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? *at this point, the new data is transferred to the r registers of both devices and stored. no other registers are af fected. * r0 ??? ??? ??? r1 figure 26. accessing the r registers of two cascaded mc1451701 devices r9 ??? ??? ??? ??? ??? ??? ???
mc1451701 motorola 21 ??? ??? ??? ??? ??? ??? 1 2 8 9 10 15 16 17 23 24 25 31 32 33 n register bits of device #2 in figure 24 n register bits of device #1 in figure 24 x x x x x n15 n8 n7 n0 n15 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 39 40 41 47 48 n8 n7 n0 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? enb clk d in * *at this point, the new data is transferred to the n registers of both devices and stored. no other registers are af fected. figure 27. accessing the n registers of two cascaded mc1451701 devices
mc1451701 motorola 22 cmos mcu d out enb clk d in device #1 mc1451701 enb clk d in optional device #2 note 2 output a (d out ) 33 k w note 1 v pd v pd v cc v dd v dd v+ notes: 1. the 33 k w resistor is needed to prevent the d in pin from floating. (the d out pin is a threestate output.) 2. this pll frequency synthesizer may be a mc145190, mc145191, mc145192, mc145200, or mc145201. 3. see related figures 29, 30, and 31. figure 28. cascading two different device types
mc1451701 motorola 23 1 2 7 8 9 10 15 16 17 18 23 24 25 26 31 32 33 34 39 40 c register bits of device #2 in figure 28 c register bits of device #1 in figure 28 *at this point, the new data is transferred to the c registers of both devices and stored. no other registers are af fected. x x x x x x c7 c6 c0 x x x c7 c6 c0 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? * enb clk d in figure 29. accessing the c registers of two different device types enb clk d in 1 2 16 17 18 20 21 22 30 31 32 39 40 41 42 43 a register bits of device #2 in figure 28 r register bits of device #1 in figure 28 x x a23 a22 a19 a18 a0 x ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 46 47 48 55 56 r9 r8 r0 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? *at this point, the new data is transferred to the a register of device #2 and r register of device #1 and stored. no other registers are af fected. * ?? ?? ?? ?? a8 figure 30. accessing the a and r registers of two different device types r14 ?? ?? ?? r13 ?? ?? ?? a9
mc1451701 motorola 24 ??? ??? ??? ??? ??? ??? ??? 1 2 8 9 10 15 16 17 23 24 25 31 32 33 r register bits of device #2 in figure 28 n register bits of device #1 in figure 28 x x x x x r15 r8 r7 r0 n15 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 39 40 41 47 48 n8 n7 n0 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? figure 31. accessing the r and n registers of two different device types enb clk d in * *at this point, the new data is transferred to the r register of device #2 and n register of device #1 and stored. no other registers are af fected.
mc1451701 motorola 25 package dimensions p suffix plastic dip (dualinline package) case 64808 d suffix sog (smalloutline gullwing) package case 751b05 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 1 8 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc1451701 motorola 26 dt suffix tssop (thin shrunk smalloutline package) case 948c03 a b pin 1 identification l 1 8 9 16 d c seating g h f m dim a min max min max inches 5.10 0.200 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0047 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.22 0.23 0.009 0.010 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 0 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimensions a and b are to be determined at datum plane u. j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 k k1 j j1 section aa a a 16x ref k 0.100 (0.004) m -t- 0.200 (0.008) m t -u- -p- plane
mc1451701 motorola 27 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 mc1451701/d
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